Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
541013 | Integration, the VLSI Journal | 2014 | 11 Pages |
Abstract
In 3D ICs, through-silicon-vias (TSVs) can suffer from cross coupling if signal integrity is not considered during the design process. In this paper, coupling between TSVs is modeled, and a chip-scale TSV shielding scheme is presented. A geometric model is developed to estimate TSV coupling. The low complexity of the geometric model makes it practical for chip-scale shield placement optimization. Two shield placement algorithms are presented and compared to standard shield placement techniques that use a high complexity circuit model of coupling. Results show that our algorithms are able to reduce the total cross coupling in a layout on average 111%/129% more than standard methods.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Caleb Serafy, Bing Shi, Ankur Srivastava,