| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 541031 | Integration, the VLSI Journal | 2013 | 7 Pages |
This paper presents a current-steering approach to implement a fast transient response low-dropout regulator (LDO) based on a current feedback amplifier (CFA) topology. The circuit does not require any internal compensation capacitor, being stable for a wide range of output load currents [0–100 mA] and a 1 μF output capacitor. The CFA consists of an open-loop voltage follower with output local current–current feedback based on a level-shifted flipped voltage follower (LSFVF) which is instrumental to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the power pass transistor results in high PSRR. Post-layout simulation results for a 0.35 μm CMOS process design reveal that the proposed LDO requires 59 μA quiescent current at no-load condition and at full-load condition has a current efficiency of 99.8%. For a 1 μF output capacitor, the maximum output voltage variation to a 0–100 mA load transient with rise and fall times of 10 and 100 ns is only 3 mV, and the PSRR is smaller than −56 dB over the entire load current range.
► This paper presents a current-steering fast transient low-dropout regulator (LDO). ► The LDO is based on a current feedback amplifier (CFA) topology. ► The circuit does not require any internal compensation capacitor. ► It is stable for a wide range of output load currents and a 1 μF output capacitor. ► Post-layout simulation results reveal high performance of the proposed LDO.
