Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology

Interconnect mis-prediction is a major problem in nano-scale design that may diminish the quality of physical design algorithms or may even result in design divergence. In this paper, a new interconnect-planning methodology based on assume and enforce strategy is presented. In this methodology, some regions of the chip are planned to provide auxiliary routing resources and improve the interconnect delay of critical nets during the floor-placement process. Each of these wealthy regions is called a highway-on-chip. The location of highways and their resources are gradually determined during the hierarchical floor-placement process. Experimental results show that the performance, timing yield, predictability and power consumption of the attempted benchmarks are improved by 13.66%, 10.02%, 20.11%, and 6.83% on average. These improvements are obtained at the cost of about 7.82% runtime overhead and less than 0.8% wirelength growth.