| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 542678 | Integration, the VLSI Journal | 2016 | 7 Pages |
Abstract
•Comments on “Dual-rail asynchronous logic multi-level implementation” are provided.•Incorrect interpretation of disjoint sum-of-products (DSOP) form is clarified.•Possibility for the occurrence of deadlock condition is elucidated.•Problems with completion detection are described.•Naïve and incorrect decomposition of NAND gates in the function block is explained.
In this research communication, we comment on “Dual-rail asynchronous logic multi-level implementation” [Integration, the VLSI Journal 47 (2014) 148–159] by expounding the problematic issues, and provide some clarifications on delay-insensitivity, robust asynchronous logic, multi-level decomposition, and physical implementation.
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Authors
P. Balasubramanian,