Design of multi-mode application-specific cores based on high-level synthesis

In a mobile society, more and more devices need to continuously adapt to changing environments. Such mode switches can be smoothly done in software using a general purpose processor or a digital signal processor. However hardware cores only can cope with both throughput and power consumption constraints. Reconfigurable hardware platforms provided by FPGA devices offer partial reconfiguration at runtime. However they require too long reconfiguration times and they cannot satisfy mobile device power consumption requirements. In this article we propose a methodology to map selected groups of DSP tasks to multi-mode cores using conventional hardware technologies.

► We propose a methodology to map selected groups of DSP tasks to multi-mode cores. ► We make use of high-level synthesis for the design of multi-mode cores. ► DFGs are processed concurrently. ► Joint ad-hoc scheduling and binding algorithm is proposed. ► Synthesis process takes care of data word-length and supports time and resource constraints.