| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 542798 | Integration, the VLSI Journal | 2012 | 8 Pages |
A new scheme of test data compression based on run-length, namely equal-run-length coding (ERLC) is presented. It is based on both types of runs of 0's and 1's and explores the relationship between two consecutive runs. It uses a shorter codeword to represent the whole second run of two equal length consecutive runs. A scheme for filling the don't-care bits is proposed to maximize the number of consecutive equal-length runs. Compared with other already known schemes, the proposed scheme achieves higher compression ratio with low area overhead. The merits of the proposed algorithm are experimentally verified on the larger examples of the ISCAS89 benchmark circuits.
► ERLC explores the relationship between two consecutive runs. ► ERLC is based on both types of runs of 0's and 1's. ► ERLC uses a shorter codeword to represent the whole second run of two equal length consecutive runs. ► A scheme for filling the don't-care bits is proposed to maximize the number of consecutive equal-length runs.
