| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 542825 | Integration, the VLSI Journal | 2009 | 9 Pages |
Abstract
In this manuscript, we introduce novel carry lookahead (CLA) and parallel-prefix architectures for the design of modulo 2n+12n+1 adders with operands in the diminished-1 number representation. The proposed architectures are based on the use of Ling carries’ computation units and they lead to faster and/or smaller adders than the already known ones that are based on the traditional carry signals.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
H.T. Vergos, C. Efstathiou,