Large scale P/G grid transient simulation using hierarchical relaxed approach

This paper proposes a hierarchical relaxed approach to analyze large scale on-chip power/ground (P/G) grids with C4 packages efficiently. Different from the existing hierarchical approach where macro models and time-consuming matrix density reduction technique are used, this novel approach uses an iterative relaxation procedure to explicitly exploit the character of boundary nodes caused by C4 bumps, which can lead to more speedup without losing any accuracy. Also, an efficient partition strategy is generated to help the new algorithm to achieve higher performance on C4 based P/G grid. Experimental results demonstrate that the new algorithm is as accurate as the existing hierarchical method while it delivers more speedup over it for C4 based P/G grid.