A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects

The delay of on-chip interconnect wiring is having an important influence on the timing performance of logic path. This is particularly true where drivers are connected through a non-negligible length of wire. If the Elmore resistance-capacitance delay model remains popular due to its simple formulation, limitations have been shown in sub-micrometer domain due to its inability in capturing input slope and shielding effects.This paper presents an analytical expression for the transition time and the switching delay of an RC interconnect, including the line input and output drivers. Based on a previously developed model of the inverter transition time and the switching delay, we propose a model of the shielding capacitance effect on the input driver. We then determine the transition time of the output driver and the switching delay of the complete structure for different size of input drivers. We validate these analytical expressions with respect to electrical simulations, on 130 and 90 nm processes, using the eldo's transmission line model.