| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 543002 | Integration, the VLSI Journal | 2006 | 6 Pages |
Abstract
A novel vertical SOI configuration has been simulated to improve the MOSFET scaling. The new structure combines the advantages of vertical MOSFET and SOI. The floating body effect of a usual SOI can be suppressed by an asymmetric source–drain configuration by connecting the source and the substrate. The optimizations on some structural parameters including silicon film thickness tsi, gate dielectric constant k and channel concentration Nb are done to improve the subthreshold characteristics and the output currents of the drain.
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Hardware and Architecture
Authors
J. Tong, X. Zou, X.B. Shen,