A technique to linearize the discrete-time parametric amplifier

This paper presents a linearization technique to reduce harmonic distortion in a discrete-time parametric amplifier (DTPA). The technique may be applied to other variants of the DTPA, such as the complementary discrete-time parametric amplifier (CDTPA), the reverse discrete-time parametric amplifier (RDTPA), and the double-complementary discrete-time parametric amplifier (DCDTPA), to achieve similar, consistent, reductions in harmonic distortion. The parametric amplifier with and without the distortion-reducing linearization scheme was simulated for a standard 0.13 μm CMOS technology, with a sampling frequency of 250 MS/s and a 1.2 V power-supply voltage. The proposed technique shows 10 dB of mean reduction in the third-harmonic for a DTPA. Experimental results show a mean reduction in the third harmonic of 6 dB for a pMOS DTPA. The results exhibit consistent reduction in distortion for almost any input amplitude and any input common-mode voltage, without reduction in gain, without reduction in drive capability, and without any extra area requirement.