Inverse Gaussian distribution based timing analysis of Sub-threshold CMOS circuits

•An accurate and flexible delay model for sub-threshold CMOS circuits is proposed.•Both combinational and sequential circuits are considered.•Fan-out effect is also taken into account.•High accuracy of our approach is achieved against SPICE Monte Carlo simulation.

Aggressive technology scaling and ultra low power constraints have resulted in less predictable device behavior complicating timing analysis/estimation. The traditional delay models fail to accurately capture the circuit behavior under such conditions. This paper proposes a novel highly accurate Inverse Gaussian Distribution (IGD) based delay model applicable to both combinational and sequential elements for sub-powered circuits. The IGD based delay estimation accuracy is demonstrated by evaluating multiple circuits, i.e., D Flip Flops (DFFs) + 8-bit Ripple Carry Adder, and 8-bit De-multiplexer (DEMUX) and Multiplexer (MUX). Our experiments indicate that the IGD based approach provides a high matching against HSPICE Monte Carlo simulation results, with an average error less than 1.9% and 1.2% for the two circuits, respectively, while sparing orders of magnitude simulation time. Moreover, the IGD model outperforms the traditional Gaussian Distribution (GD) model by providing 6 × better average accuracy with no extra simulation time overhead.