Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
545484 | Microelectronics Reliability | 2009 | 5 Pages |
Abstract
The breakdown of 35 Å and 70 Å thick NMOS and PMOS silicon Gate oxides used in 1.8 V and 3.3 V BCD8 Smart Power technological node was investigated in this work. Both voltage to breakdown, from DC down to the ESD time domain, and time-dependent breakdown analysis have been carried out. We present also the evidence that breakdown is not affected by cumulative stress and it is mainly driven by voltage stress.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
A. Tazzoli, L. Cerati, A. Andreini, G. Meneghesso,