High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems

In this paper a hardware architecture of scalar multiplication based on Montgomery ladder algorithm for binary elliptic curve cryptography is presented. In the proposed architecture, the point addition and point doubling are performed in parallel by only three pipelined digit-serial finite field multipliers. The structure of multiplier with a low critical path delay is based on a parallel and independent computation of multiplication by power of the variable polynomial. The inversion operation is implemented by using an efficient architecture of Itoh–Tsujii inversion algorithm. To maximize the performance of the scalar multiplier, a clock switch block is used to manage the clock signal so that the circuit operates at its maximum frequency at different steps of the Montgomery ladder scalar multiplication algorithm. Implementation results of the proposed architecture on Virtex-5 XC5VLX110FPGA show that the execution time of the scalar multiplication for binary finite fields GF(2163) and GF(2233) are 5.08 µs and 6.84 µs respectively, which are better than those of other similar works.