Electro-thermal high-level modeling of integrated circuits

Operating temperature and temperature gradients are of critical concern in the design of planar integrated circuits (ICs) and are bound to be exacerbated in the upcoming 3D technologies. However, a thermal aware design of ICs allows thermal issues to be kept to the minimum. Previously, a simulator integrated in the Cadence®Cadence® environment that allows electro-thermal simulations to be carried out at a transistor level has been presented. Since this simulator is based on the use of the Verilog-A®Verilog-A® hardware description language, electrothermal simulation can be performed as long as high-level electro-thermal models are provided. In this paper, a methodology used to build such high-level electro-thermal models compliant with this simulator is detailed and simulation results at low and high level are compared.