A finite state machine based fault tolerance technique for sequential circuits

•A finite state machine (FSM) based fault tolerance technique is proposed.•It is based on adding redundant equivalent states to protected states.•Few states with high probability of occurrence are protected.•Hamming distance between protected states codes needs to be 3.•Lower failure rates and reduced area overhead are achieved in comparison to other techniques.

With technology advancement at the nanometer scale, systems became more subjected to higher manufacturing defects and higher susceptibility to soft errors. Currently, soft errors induced by ion particles are no longer limited to a specific field such as aerospace applications. This raises the challenge to come up with techniques to tackle soft errors in both combinational and sequential circuits. In this work, we propose a finite state machine (FSM) based fault tolerance technique for sequential circuits. The proposed technique is based on adding redundant equivalent states to protect few states with high probability of occurrence. The added states guarantee that all single faults occurring in the state variables of highly occurring states or in their combinational logic are tolerated. The proposed technique has minimal area overhead as only few states need protection.

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