Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
548923 | Microelectronics Reliability | 2015 | 5 Pages |
Abstract
Ultra-low effective oxide thickness (EOT) Ge MOS devices with different HfAlO/HfON stacks and sintering temperatures are investigated in this work. The suppression of gate leakage current and improvement of reliability properties can be achieved by either stacked gate dielectrics or a low sintering temperature. Especially, the qualities of the interface and high-k gate dielectric in Ge devices are significantly improved through a low sintering temperature. A 0.5 nm HfAlO/2.5 nm HfON gate stack and a sintering temperature at 350 °C are the suitable conditions to achieve low EOT, gate leakage, and good reliability for Ge MOS devices.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Wei-Fong Chi, Kuei-Shu Chang-Liao, Shih-Han Yi, Chen-Chien Li, Yan-Lin Li,