Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6942163 | Integration, the VLSI Journal | 2018 | 8 Pages |
Abstract
This paper presents a clock and data recovery (CDR) topology that can adjust the power consumption with its input bit-rate. Current-mode structures are utilized to control the power consumption. The system is comprised of a phase detector, a charge pump, a second-order filter, a voltage-to-current converter, a bias controller, and a current controlled oscillator. In order to attain an ultra-low power profile, subthreshold source-coupled logic (STSCL) is used to implement the system blocks. A modified version of low-voltage current-mirror is proposed and utilized to improve the thermal stability of the CDR structure. The proposed current mirror improves the oscillator frequency variation more than 20 times. The CDR is simulated in 90â¯nm standard CMOS process with VDDâ¯=â¯1â¯V. It can recover clock frequencies between 1â¯MHz and 25â¯MHz. The corresponding power consumption is between 195â¯nW and 450â¯nW, and the measured deterministic-jitter is less than 100â¯ns.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
J. Ahmadi-Farsani, H. Sadjedi, M.B. Ghaznavi-Ghoushchi,