A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS

A 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) was implemented in a 14 nm SOI FinFET CMOS technology, achieving 59.59 dB SNDR at 50 MS/s while consuming 41.3 µW power. Several techniques were used to increase the energy efficiency while ensuring the linearity. First, a segmented architecture with a 5-bit coarse ADC and an 11-bit fine ADC was used. The aligned Switching with Skip (ASS) method was used to generate the five MSBs of the fine ADC from the computed coarse ADC bits, saving 58% switching power compared with non-segmented architecture with merged capacitor switching (MCS) method. Second, VCM-based MCS scheme is used for SAR bit resolving, saving 85.72% switching power compared with traditional SAR switching. Third, the dual supply mode with analog at 0.8 V and digital at 0.4 V was used. This reduces the total digital logic power consumption by 23% comparing with that using the single supply at 0.8 V. The differential architecture was used to minimize the common mode non-idealities. The proposed ADC has been implemented in a 14 nm SOI FinFET technology and achieved a peak Figure of Merit (FoM) of 1.07 fJ/Conversion-step with simulation results.