Improving performance of FPGA-based SR-latch PUF using Transient Effect Ring Oscillator and programmable delay lines

In this paper, we propose a new structure of SR-Latch Physically Unclonable Function (PUF) based on Transient Effect Ring Oscillator (TERO). Our proposed TERO-based scheme combines the features of two different programmable delay lines (PDLs) and generates the response bits by comparing the number of oscillations of the SR-Latches during the metastable state. The proposed scheme reduces the impact of environmental noise to increase the reliability of the response bits. Also, our proposed area-efficient PUF architecture has low complexities and hence consumes low power consumption as compared to the counterparts. Moreover, we investigate the impact of systematic variation on the uniqueness of the response bits. We have used an optimized placement (in term of area cost) for the proposed structure and implemented our proposed scheme on the Spartan3 FPGA boards. The implemented structure demonstrates considerable performance metrics such as the uniqueness of 49.32%. In addition, the proposed structure provides higher reliability when tuned with PDLs. Hence, the need for complex error correcting codes is reduced. This makes the scheme appropriate for low-cost authentication and cryptographic applications.