Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling

This paper addresses the issue of power-aware test scheduling of cores in a System-on-Chip (SoC). While the existing approaches either use a fixed power value for the entire test session of a core or cycle-accurate power values, the proposed work divides the power profiles of cores into fixed-sized windows. This approach reduces the number of power values to be handled by the test scheduling algorithms while reducing the amount of pessimistic over-estimations of instantaneous power consumption. As a result, the power model can be integrated with more exhaustive meta-search techniques for generating power constrained test schedules. In this paper, the proposed power model has been integrated with a Particle Swarm Optimization (PSO) based 3-dimensional (3-D) bin packing technique to generate test schedules. Experimental results prove the quality of the approach to be high compared to the existing scheduling techniques.