Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6944858 | Microelectronics Journal | 2018 | 10 Pages |
Abstract
A 10-bit 100â¯MS/s energy-efficient successive-approximation analog-to-digital converter (SAR ADC) is presented in this paper. In order to improve the conversion rate and reduce power consumption as well, a modified spilt-capacitor VCM-based switching scheme is proposed. By utilizing the LSB capacitors to obtain the last-bit, the proposed switching scheme could decrease the area of capacitive DAC. Moreover, by modifying the switching behaviors of the most significant bit (MSB) and 2nd-MSB, the conversion rate could be improved. The prototype SAR ADC fabricated in 0.18â¯Î¼m CMOS achieves 53.68â¯dB SNDR and 62.85â¯dB SFDR at 100â¯MS/s sampling rate. The active area of the core is 0.216â¯mm2. It consumes 5.23â¯mW with 1.8â¯V supply, resulting in a Walden figure of merit (FoM) of 123.2 fJ/conversion step.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Rui Ma, Lisha Wang, Dengquan Li, Ruixue Ding, Zhangming Zhu,