Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6944947 | Microelectronics Journal | 2018 | 12 Pages |
Abstract
A wideband 2-3â¯GHz three-stage low noise ampliï¬er (LNA) featuring current reuse, cascaded L-type input matching network (IMN), and optimized multiple gated transistors method (MGTR) using 0.18-μm CMOS technology is presented in this paper. The current-reused topology is employed in the first two stages to reduce power consumption. For a wideband input matching, the common gate (CG) topology is adopted. Moreover, the cascaded L-type IMN composed of two single L-type networks cascaded in series is proposed for the first time. To improve the linearity performance, the optimized MGTR taking both transconductance gm and third-order nonlinear coefficient gmâ³ into consideration is proposed and applied to the output stage. The proposed LNA presents a maximum power gain of 28.0â¯dB, an input matching across 1.8-5.8â¯GHz and a high third-order input intercept point (IIP3) of â9.89â¯dBm. A noise figure (NF) of 3.1-3.5â¯dB is obtained in the required band with a power dissipation of 6.49â¯mA from a 3â¯V power supply.
Keywords
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Guoxiao Cheng, Zhiqun Li, Lei Luo, Zengqi Wang, Xiaodong He, Boyong He,