A novel biasing technique for low phase noise voltage controlled oscillators

This paper proposes a new biasing technique for LC-based voltage controlled oscillators to improve the phase noise performance while ensuring the current variations to be within an acceptable range. The proposed technique uses a feedback loop and a LDO to generate, sense, and regulate the output current. The oscillator has 33.3% tuning range around a center frequency of 2.4 GHz. The proposed design achieves −127.2 dBc/Hz phase noise at 1 MHz offset from 2.25 GHz while consuming 3.36 mA from a 3.3-V supply. The circuit was implemented in 65 nm UMC CMOS process. The results show that the circuit has FoM of −183.8 dBc/Hz and FoMT of −194.5 dBc/Hz at 1 MHz offset, and the current variation across PVT is within +68 µA to −63 µA range.