Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6945194 | Microelectronics Journal | 2017 | 8 Pages |
Abstract
This paper implements a 10-bit segmented Dual-Sampling SAR ADC for a WPT system. To solve the mid-code problem of the Dual-Sampling structure and improve the linearity, a segmented structure is adopted in capacitive DAC. A new switching scheme is proposed for MSBs decisions to skip some of the unnecessary switching steps. This ADC is applied to digitize analog inputs of the different sub-blocks of the WPT system. Applying these techniques reduces the unit capacitor size, as well as the power consumption while improving the linearity of the system. The overall system achieves 9.8 ENOB at 1 MS/s conversion speed and consumes 19.6 μA from 3 V supply voltage. DNL and INL for this structure are measured to be â0.63-0.56 and â0.85-0.79 LSB respectively. The active area of the ADC in 0.18 μm CMOS process is 760 Ã 430 μm2.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Behnam Samadpoor Rikan, Hamed Abbasizadeh, Young-Jun Park, Hye-Yeong Kang, SangYun Kim, YoungGun Pu, Minjae Lee, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee,