On-chip implementation of a low-latency bit-accurate reciprocal square root unit

Many applications such as gaming, digital signal processing and communications systems, require computation of the reciprocal square root operation (RSR). Although several architectures have been reported for computing the RSR operation, these are mainly focused on accelerating high-precision floating-point units. In mobile-device implementations, fixed-point (FxP) units are preferred due to their low computational cost and power consumption. This article presents an on-chip implementation of a bit-accurate, FxP-RSR unit using a 130 nm CMOS process. The proposed architecture is based on a piecewise-polynomial approximation in a reduced range of the RSR function and the Newton-Raphson method. Experimental results show that the manufactured chip exhibits lower latency and less power consumption than existing standard-cell-based implementations. These characteristics make the proposed chip a useful silicon intellectual property suitable for embedded applications where low power, low latency, and low hardware cost is required.