A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS

A high-speed multi-phase clock generator with duty cycle imbalance correction is proposed. Multiplexers are added between every two registers to correct the imbalance, hence to reduce the deviation of duty cycle and magnitude among multi-phase clocks while maintaining a high operating frequency and low power consumption. An eight-phase 12.5% duty cycle clock generator is designed and fabricated using a 0.13 μm RF CMOS process. It's able to generate multi-phase clocks with less than 1° duty cycle imbalance and has a measured operating frequency up to 2.5 GHz with a maximum power consumption of 2.4 mW from a 1.2 V supply while occupying a silicon area of 65 μm × 100 μm.