A fast temperature-aware fixed-outline floorplanning framework using convex optimization

With aggressive scaling of CMOS technology, it is essential to consider chip temperature in all design levels of digital systems to improve chip reliability and leakage power consumption. In this paper, we present a two phase fixed-outline floorplanning framework that attempts to reduce the peak-temperature of the chip. The first phase distributes evenly the available dead space between the floorplan blocks of a chip, so as to reduce the peak-temperature. The second phase employs a two-stage convex optimization formulation to perform fixed-outline floorplanning such that minimizes the peak-temperature while satisfying physical constraints. To mitigate the time and computational complexity of capturing the temperature behavior, we present a less computational expensive analogous formulation that approximates the temperature of a block by its corresponding power density. Although, the corresponding power density formulation exhibits lower complexity the experimental results demonstrate its high degree of accuracy. Moreover, this formulation manages to achieve significant improvements in terms of peak-temperature and runtime for almost all of the test cases. We investigate the trade-off between peak-temperature and area as well and provide conditions that result in a reasonable reduction of peak-temperature with minimum increase of the dead space.