A wet etching approach for the via-reveal of a wafer with through silicon vias

The process of via-reveal on the wafer backside is one of key steps for a successful implementation of 3D-IC stacking using the TSV technique. Instead of using a full chemical mechanical polish (CMP) or a dry etch process, we proposed a method of full wet etching. The solutions of HF/HNO3 and tetramethyl ammonium hydroxide (TMAH) are used. Based on the full wet etching mechanism of silicon, we done some experiments to obtain the satisfied etching rate, selectivity and etching profile with optimized parameters. Using the approach, the via-reveal process was conducted for wafers with different incoming remain silicon thickness (RST) profiles. The wet etching results demonstrated that the exposed tips of TSVs were in good shape and had no damage in the liner oxide and Cu metal. The height of exposed TSV can be controlled very well and the etched silicon surface is smooth and uniform. So the present full wet etching process is well-controlled, efficient and cost effective method.163