A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

•A new domino circuit technique is proposed for wide gates.•Difference between voltages across the pull down network is used to generate output.•The proposed technique decreases leakage and increases noise immunity.•The proposed circuit is superior to existing designs especially for wide gates.

In this paper, a new leakage-tolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant delay increment for wide fan-in gates. The main idea in the proposed circuit is using sense amplifier for sensing the difference between voltages across the pull down network (PDN). This strategy provides correct output. In the proposed technique, therefore, the voltage swing of the dynamic node can be reduced to decrease the power consumption caused by the heavy switching capacitance in wide fan-in gates. The simulation is provided with 64-bit wide OR gates using a 90 nm CMOS technology model. The simulation results are compared with that of standard domino circuits at the same delay, and 35% power consumption reduction and 2.31× noise-immunity improvement are observed.