A statistics-based digital background calibration technique for pipelined ADCs

•The proposed calibration technique continuously operates in the background during normal data-conversion operation of pipelined ADCs.•This scheme digitally mitigates gain, second-order, and third-order errors in the digital output of the pipelined ADCs.•The presented method just requires one integrator at the sampling-rate of pipelined ADCs to mitigate conversion errors.•This technique is not sensitive to the residue amplifier offset.•This method can be used to simplify analog circuit design in pipelined ADCs.

This paper introduces a digital background calibration technique for pipelined analog-to-digital converters (ADCs). The proposed method continuously measures and digitally corrects conversion errors resulting from residue amplifier gain error and nonlinearity. It is based on modulation of the residue voltage using a pseudorandom-noise sequence (PN). A least-mean-squares (LMS) algorithm is utilized to correct conversion errors arising from the residue amplifier non-idealities. Besides, a new statistics-based digitized residue distance estimation (DRDE) algorithm is proposed that allows the LMS algorithm to operate in the background without interrupting the normal operation of the ADC. The DRDE method extracts the residue amplifier non-idealities by evaluating the digitized residue voltage probability density function (PDF). Behavioral simulation results verify the usefulness of the proposed calibration technique and show that the signal-to-noise-and-distortion-ratio (SNDR) is improved from 43 to 71.9 dB, in a 12-bit pipelined ADC.