Nano-CMOS thermal sensor design optimization for efficient temperature measurement

•A robust design flow is proposed to design and characterize nano-CMOS based thermal sensors.•An optimization methodology is presented for fast design space exploration of thermal sensors.•A modified Stochastic Gradient Descent (SGD) algorithm is presented for thermal sensor optimization.•A 45 nm RO based thermal based sensor is designed at the layout level and optimized.•A statistical analysis on the impact of process variation on the performance of the thermal sensor is presented.•A perspective comparison of similar designs is also presented.

We present a novel and efficient thermal sensor design methodology. The growing demand for power management on VLSI systems drives the need for accurate thermal sensors. Conventional design techniques for on-chip thermal sensors in nanometer technologies consume expensive design iterations and result in increased power consumption and area overhead. Power-efficient, high-sensitivity thermal sensors are important for reducing the thermal stress on the systems or circuits which are being monitored. The proposed design flow methodology, which incorporates a stochastic gradient descent (SGD) algorithm, optimizes the power consumption (including leakage) of IC subsystems. An illustration of the proposed design methodology is presented using a ring oscillator (RO) based on-chip thermal sensor which was designed using 45 nm CMOS technology. The RO based thermal sensor has a resolution of 0.097 °C/bit. Experimental tests and analysis of the design methodology on a full layout-accurate parasitic netlist of the RO demonstrate the applicability of our methodology towards optimization of the power consumption with temperature resolution as a design constraint. A reduction of power consumption by 52% with a final area of 1389.1μm2 is obtained.