Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing

In this work, we propose a technique to reduce switching activity while keeping leakage current under control during testing by extracting don't cares from a completely specified pattern set, and using the X bits to convert original vectors into low power vectors by a dictionary based approach. We also investigate the possibility of reducing test set length, maintaining fault coverage, by performing a tradeoff between test set volume and power. Experiments on ISCAS89 benchmark circuits validate effectiveness of our work. We could achieve an average reduction of 84.78% in dynamic power and 6.52% in leakage power for pattern set generated by the ATPG tool Atalanta. Similar savings could also be achieved on test set generated by the commercial ATPG tool Tetramax.

► In this work, we use an extended version of the don't care identification technique. ► The identified don't cares are utilized to align each pattern with low-leakage ones. This reduces dynamic and leakage power in both non-scan and scan circuits. ► A new pattern selection algorithm to identify the minimal set of low-power patterns to achieve the desired level of fault coverage. ► A Particle-Swarm Optimization (PSO) based reordering technique for the test vectors to reduce power further. ► A pattern replacement scheme to reduce test length at the cost of increase in test power.