Characterization of metal contact to III–V materials (Mo/InGaAs)

•A method to reduce the contact resistance between metal and semiconductor is proposed.•The method consists of the repetition of oxide growth/etching to cure damaged surface.•The repetition of oxide growth followed by etching is used to cure damaged surface.•The technic was applied to Molybdenum/InGaAs interface on TLM test structure.•We report a contact resistivity of 0.71 Ω μm2.

The CMOS device channel material for sub-10 nm dimensions has been identified to be major challenge as per the International Technology Roadmap for Semiconductors (ITRS). Among the options that are defined by ITRS roadmap is the high mobility III–V based channels. In this paper, we report on new III–V materials showing great potential in achieving nanometric scale transistors in support of applications that require operating at 0.3–0.5 V. In the first phase of this research, a special focus was given to Molybdenum/InGaAs contacts in order to set up basic unit processes and characterization techniques. Indeed, the electrical measurement were performed and linked to the interface morphology characterized by Scanning Electron Microscopy (SEM), Scanning Transmission Electron Microscopy (STEM) and High Resolution Transmission Electron Microscopy (HRTEM). Kelvin structures of Molybdenum over InGaAs were fabricated as test structures to measure the contact resistance and resistivity of the aforementioned interface. Plasma damages induced during the fins definition by reactive ion etching are known to significantly increase the contact resistivity in III–V based finFET. The digital etch technique is implemented on an unexposed plasma damages sample in order to assess the compatibility of this technique with a finFET process flow. The first set of electrical measurements gives a contact resistance of 0.71 Ω μm2 competitive with existing Mo/InGaAs contact resistance, revealing the compatibility of the digital etch cleaning technique with common MOSFET process flow.

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