Optimization and evaluation of the size-free integration process for MEMS-IC assembly with high yields and high efficiency

•Chip to wafer self-alignment phenomenon was successfully identified into 3 steps.•Hybrid chip-dicing process was developed for a better yield and alignment accuracy.•Surface activated bonding was introduced for wafer level chip transfer at room temperature.•Practically valuable for size-free and flexible MEMS-IC integration in wafer scale.

Wafer level chip scale package (WLCSP) is one of the most promising methods for the integration of micro-electromechanical systems (MEMS) with integrated circuits (IC). In our previous works, we have successfully developed a 2-step approach by using a carrier wafer for size-free MEMS-IC integration. This approach exhibits both excellent process flexibility and high efficiency. This approach has been proved practically valuable when compared to chip to wafer (C2W) bonding or wafer to wafer (W2W) bonding. For the improvement of above approach, the phenomenon of the chip to carrier wafer self-alignment was investigated in this work. The process parameters and the chip-dicing processes, which may affect yields and accuracy of the self-alignment, were analyzed. A hybrid process was then proposed for chip-dicing to reduce the process cost as well as to decrease the exhaust of greenhouse gases. Moreover, a surface activated room temperature bonding process was introduced and optimized for transferring of above chips from the carrier wafer to a target wafer with less damage to those chips. A full size-free MEMS-IC integration process was finally demonstrated, and then evaluated from both electrical and mechanical points-of-view.

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