Advanced wafer thinning technology and feasibility test for 3D integration

The ultra-thinning less than 0.5 μm of total thickness variation (TTV) within 300 mm wafer has been developed for the wafer-on-a-wafer (WOW) application. TTV was controlled by measuring wafer thickness and parallelity between grinder and wafer surface, called Auto-TTV method. Surface treatment to remove damage layer such as defects and non-crystalline layer was also developed. For the ultra-thinning less than 10 μm in wafer thickness, no significant device degradation in the high performance 45 nm node CMOS and FRAM memory was revealed. The impact of ultra-thinning processes on strained transistors and Cu/low-k multilevel interconnects as well as FRAM memory is described. Properties examined include stack chain resistance of Cuα interconnects as well as Ion-Ioff, threshold voltage shift, and junction leakage of transistors for CMOS logic, and switching characteristics for FRAM before and after thinning. It was found that the electrical properties were not affected by bonding, thinning and debonding process, indicating good feasibility of 3D stacking integration.

Graphical abstractFigure optionsDownload full-size imageDownload as PowerPoint slideHighlights► Development of automatically feed-back process for improving total thickness variation (TTV) of Si wafer. ► Impact of ultra thin wafer on strained transistors and Cu/low-k interconnects as well as FRAM memory for 3D-IC. ► Characterization of CMOS transistors before and after thinning. ► Characterization of switching property of FRAM before and after thinning.