A novel chip-to-wafer (C2W) three-dimensional (3D) integration approach using a template for precise alignment

This paper reports a novel chip-to-wafer (C2W) three-dimensional (3D) integration approach using a template for precise alignment. The key unit process steps, including template fabrication, chip edge definition, C2W alignment and bonding, are investigated. To demonstrate this C2W approach, benzocyclobutene (BCB) and Cu are selected as the starting materials for template and bonding, respectively. Wafers with Cu daisy chains are fabricated for both the chip and host wafer. Individual chips are produced by a 2-step process: defining the chip edges and dicing. All individual chips are aligned to the host wafer with a BCB template, followed by a wafer-level Cu–Cu bonding process. An alignment accuracy of approximately 2 μm is achieved and a good Cu–Cu bond interface is observed with Cu grain-growth across the bonding interface. This C2W 3D integration approach has the potential for low cost and high throughput fabrication of multi-layer high-performance 3D systems.

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