CMP process development for the via-middle 3D TSV applications at 28 nm technology node

A through-silicon-via (TSV) chemical mechanical polishing (CMP) process with three polishing steps, including Cu polishing, Cu barrier/isolation layers polishing and dielectric SiN stop layer polishing, has been proposed to form the 70 μm deep with 10 μm diameter size via-middle TSV structures at 28 nm technology node. The integrated process optimizations of pre-TSV CMP anneal and electrochemical deposition (ECD) of Cu have been evaluated to enlarge TSV CMP process window and prevent the formations of the Cu extrusion and voids post-back-end-of-line (BEOL) processes. Less than 150 Å of within wafer and within lot inter-layer dielectric (ILD) mapping thickness range control and less than 100 Å Cu extrusion level without voids post-TSV capping layer deposition can be achieved as implementing 400 °C for 10 min pre-TSV CMP annealing condition and uniform TSV ECD profile electroplated in less impurity chemical solution.