| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 539493 | Microelectronic Engineering | 2012 | 4 Pages |
Abstract
PVD CuMn self-forming barrier (SFB) approach was investigated on 300 mm wafers as an alternative to conventional PVD Ta/Cu metallization. Cu fill on very aggressive dual damascene features targeted for beyond 32 nm node was evaluated along with integrated electrical and reliability performance on low-k (k = 2.6) interlayer dielectric (ILD).
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Tejaswi K. Indukuri, Rohan N. Akolkar, James S. Clarke, Arda Genc, Florian Gstrein, Michael C. Harmes, Barbara Miner, Feng Xia, Daniel J. Zierath, Sridhar Balakrishnan,