Impact of increased resistive losses of metal interconnects upon ULSI devices reliability and functionality

The impact of increasing resistive losses of on-die metal interconnects upon device reliability and functionality has been studied. The signal waveforms experimentally measured at the far-end of on-die transmission lines (45 nm CMOS technology test chip) with various ratios between the level of resistive losses and the characteristic impedance of the line, have been taken as a basis for calculations of Age parameters from Berkeley Reliability Tools, and for calculations of CMOS inverters dynamic power dissipation. The results reveal that the high level of resistive losses accelerates the device degradation caused by Hot Carrier Injection (HCI) wearout mechanism and leads to increased power consumption. Therefore, the resistive losses of on-die transmission lines should be also regarded as a reliability issue.