Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
539892 | Microelectronic Engineering | 2010 | 8 Pages |
Abstract
Direct wafer bonding and thinning technologies are now extensively used in combination to produce SOI wafers (silicon-on-insulators) or innovative engineered substrates. Emerging demands of new functionalities at the material or device level for 3D integration have allowed increasing the level of maturity of these technologies. This paper will review the physics of wafer direct bonding and its implementation for vertical integration devices of processed strata with vertical interconnects.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Pierric Gueguen, Caroline Ventosa, Léa Di Cioccio, Hubert Moriceau, François Grossi, Maurice Rivoire, Patrick Leduc, Laurent Clavelier,