| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 540473 | Microelectronic Engineering | 2011 | 4 Pages |
A planar SONOS capacitor was used to optimize different parameters of the gate stack, in view of integration in a 3D cell. It is found that a poly-Si substrate strongly degrades the channel mobility but program and retention are not compromised. The ONO stack is found to scale down to 3/4/5 nm for tunnel oxide/trapping nitride/blocking oxide, respectively. FUSI gate could be an interesting option to improve the erase operation.
Graphical abstractFigure optionsDownload full-size imageDownload as PowerPoint slideHighlights► SiO2/Si3N4/SiO2 (ONO) gate stack thickness/recipes optimization towards 3D SONOS memory cell optimization. ► Investigation of the influence of different polysilicon substrates influence on memory operation. ► Use of Fully Silicided gate (FUSI) for erase improvement.
