Ultra-dense silicon nanowires: A technology, transport and interfaces challenges insight (invited)

We present the integration scheme we have optimized to fabricate very short gate length MOSFETs with 2D and 3D arrays of silicon nanowires (NW) and higk-k/metal gate stacks. Aggressively scaled NWs with sub-5 nm diameters are obtained. In particular, we report a 3D matrices technology with up to 13 levels of stacked single-crystal Si nanowires that can be most interesting for memory applications. In addition, we present a careful study of the electrical properties of such devices. Our electrical measurements reveal that the NWs’ size, shape and surface treatment have a significant influence on transport properties. We identify peculiar transport and interface properties and we show that surface effects are significant for diameters equal or lower than 20 nm. The use of nanowires (whatever the process) in standard sub-11 nm CMOS nodes circuits will depend mainly on lithography progress in the coming years, but also on contact and metal interconnects. Ultra dense 3D arrays of Si nano-wires can however be fabricated in R&D facilities for high current, ultra-dense transistors or capacitors, sensors and NAND flash memories purposes. They are also useful for mobility and gate dielectric/nanowire interface characterization.

Graphical abstractElectrical measurements reveal that the NWs’ size, shape and surface treatment have a significant influence on transport properties. We show that surface effects are significant for diameters equal or lower than 20 nm. Morover, we show how ultra dense 3D arrays of Si nano-wires can however be fabricated up to 13 levels with R&D facilities for high current, ultra-dense transistors or capacitors, sensors and NAND flash memories. purposes. They are also useful for mobility and gate dielectric/nanowire interface characterization.Figure optionsDownload full-size imageDownload as PowerPoint slideHighlights► Aggressively scaled NWs transistors with sub-5 nm diameters and hight-k/metal gate are obtained. ► 3D NW matrices technology with up to 13 levels of stacked single-crystal Si nanowires is presented. ► Our electrical measurements reveal that the NWs’ size, shape and surface treatment have a significant influence on transport properties.