Study of CVD nanowire high-k metal interface quality for interconnect level MOS devices

We report a study of low temperature gate stack on silicon nanowires compatible with Back-End-Of-Line (BEOL) integration. The same gate stack is deposited at low temperature on Si nanowires obtained thanks to either Chemical Vapor Deposition (CVD) or Selective Epitaxial Growth (SEG) in patterns. Gate stack characterization on CVD nanowires (NWs) shows low leakages and good agreement with simulated curves without interface states. A dramatic decrease of the capacitance in accumulation region and faster electron generation are observed and attributed to NW defects. In contrast, SEG devices reveals lower capacitance decrease with frequency but higher interface state density of about 1013 cm−2.

Graphical abstracWe report a study of low temperature gate stack on silicon nanowires compatible with Back-End-Of-Line (BEOL) integration. The same gate stack is deposited at low temperature on Si nanowires obtained thanks to either Chemical Vapour Deposition (CVD) or Selective Epitaxial Growth (SEG) in patterns. Based on I(V) and C(V) measurements, devices electrical properties are compared.Figure optionsDownload full-size imageDownload as PowerPoint slideHighlights► Study of a low temperature high-k metal gate stack on guided CVD nanowires compatible with BEOL or 3D integration. ► Comparison of the potentialities between CVD and SEG for MOSFET applications. ► Studied CVD NWs have a better interface quality with the same gate stack than SEG NWs, but CVD NWs suffer from a degraded mobility, which decreases their capacitance value with increasing frequency.