Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO2 formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO2–SiO2 intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.

Graphical abstractIn gate-first and gate-last process flows, a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon.Figure optionsDownload full-size imageDownload as PowerPoint slideHighlights► Epitaxial strontium oxide (SrO) layers are integrated in TiN/HfO2 gate stacks on Si. ► In a gate-last process, SrO passivates Si. ► In a gate-first process, SrO triggers interfacial silicate formation. ► Equivalent oxide thickness of 5–6 Å is achieved, with further scaling potential. ► Effective workfunction is suitable for n-channel transistors.