| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 540528 | Microelectronic Engineering | 2011 | 4 Pages |
Abstract
Threshold voltage (VT) and mobility (μ) shifts due to process related variability and Negative Bias Temperature Instability are experimentally characterized in pMOSFETs. A simulation technique to include the time-dependent variabilities of VT and μ in circuit simulators is presented and used to evaluate their effects on CMOS inverters performance. The results show that mobility degradation under NBTI stresses could have to be considered for the evaluation of the circuit performance after device aging.
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
N. Ayala, J. Martin-Martinez, E. Amat, M.B. Gonzalez, P. Verheyen, R. Rodriguez, M. Nafria, X. Aymerich, E. Simoen,