On the impact of the Si passivation layer thickness on the NBTI of nanoscaled Si0.45Ge0.55 pMOSFETs

The negative bias temperature instability (NBTI) of nanoscaled Si0.45Ge0.55 pFETs with different thicknesses of the Si passivation layer (cap) is studied. Individual discharge events are detected in the measured threshold voltage shift (ΔVth) relaxation traces, with exponentially distributed step heights. The use of a thinner Si cap is shown to reduce both the average number of charge/discharge events and the average ΔVth step height. To qualitatively explain the experimental observations, a simple model including a defect band in the dielectric is proposed.

Graphical abstractThe NBTI reliability of nano-scaled Si0.45Ge0.55 pFETs was studied as a function of the Si cap thickness. Individual discharge events are visible in the ΔVth relaxation traces, with exponentially distributed step heights. The average number of discharge events follows the typical NBTI dependences on stress time and voltage observed for the total ΔVth on large area devices. The use of a thinner Si cap on SiGe was found to dramatically reduce the average number of discharge events and the average ΔVth step height (η), confirming this technology to be extremely promising also for nanoscaled device reliability. A simple model including a defect band in the dielectric can qualitatively explain the experimental observation, suggesting that fewer defects located on the gate side of the dielectric are accessible by the channel holes when reducing the Si cap thickness, thanks to a favorable Fermi energy alignment.Figure optionsDownload full-size imageDownload as PowerPoint slideHighlights► The NBTI of nano-scaled Si0.45Ge0.55 pFETs was studied as a function of the Si cap thickness. ► Individual discharge events are visible in the ΔVth relaxation traces, with exponentially distributed step heights. ► The average number of discharge events follows the typical NBTI dependences on stress time and voltage. ► The use of a thinner Si cap reduces both the average number of discharge events and the average ΔVth step height (η) ► Fewer defects located on the gate side of the dielectric are accessible by channel holes when using a thin Si cap.