| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 540535 | Microelectronic Engineering | 2011 | 4 Pages |
Abstract
Identification of electron trap location in HfO2/interface-layer (IFL) of poly-Si/TiN/HfO2/SiO2 gate-stacked MOSFETs is successfully demonstrated through analysis of low-frequency noise and PBTI characteristics with respect to nitrogen incorporation into the gate dielectrics in fabrication process. It is found that the electron trap existing in the bulk-IFL dominantly degrades low-frequency noise (LFN) and positive bias temperature instability (PBTI). The pre-existing electron trap is considered to be generated by N incorporation into the IFL in the fabrication process of gate-first process.
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
T. Matsuki, R. Hettiarachchi, W. Feng, K. Shiraishi, K. Yamada, K. Ohmori,