Evaluation of a PECVD advanced barrier (k = 3.7) for 32 nm CMOS technology and below

An advanced dielectric barrier proposed for sub-45 nm CMOS technology nodes is firstly characterized on 300 mm full sheet wafers. The barrier is a bi-layer deposited by PECVD. The copper diffusion barrier property is ensured by a depositing dense initiation layer with the efficiency of a standard SiCN barrier (k = 5.0). The top layer, thicker, with lower density, enables the decrease of the barrier k-value to 3.66 and plays the role of etch stop layer. Combined with a PECVD porous a-SiOC:H dielectric (k-value = 2.5), the advanced dielectric barrier is successfully integrated in a C65 dual damascene architecture reaching a 3% gain in RC. A high via chain resistance yield is evidence of good via opening. Finally, the advanced barrier shows the same electromigration performance than the standard SiCN barrier.