Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
540817 | Microelectronic Engineering | 2007 | 6 Pages |
Abstract
As IC dimensions scale down to the 32 nm technology node, interconnect is more than ever the most limiting factor affecting overall circuit performance. The influence of all involved process parameters were studied as a function of target application through electromagnetic and time domain simulations, and compared to the impact of driver characteristics. As a result, an optimization of the BEOL stack was performed to propose process and material recommendations meeting electrical specifications for most circuit applications.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
A. Farcy, M. Gallitre, V. Arnal, M. Sellier, L. Guibe, B. Blampey, C. Bermond, B. Fléchet, J. Torres,